Chips
Fingerprint SoCs with the matcher on-chip, face algorithm processors, QR decode engines and a financial-grade crypto coprocessor — the first layer of every product we ship, and of many we don't.
All 10 chip SKUs
| SKU | Positioning | Key values | Link |
|---|---|---|---|
| AS608 | Fingerprint security SoC — matcher runs on-chip | In-house DSP matching · capacitive array interface · SPI/UART/USB | AS608 → |
| AS618 | Fingerprint module controller companion | Slim module builds · host-companion role · SPI/UART | AS618 → |
| AS578 | Fingerprint algorithm chip, mid-tier performer | Algorithm-heavy AS-family member · industrial access class | AS578 → |
| AS801 | AI biometric engine chip — 2026 generation | Biometric + QR decode fusion on one die · multimodal terminals | AS801 → |
| AS732 | Rolling-shutter QR decode SoC | Cortex-A5 dual core 780 MHz · USB/serial/keyboard · 99.9%+ decode class | AS732 → |
| AS733 | Global-shutter QR decode SoC | Motion-tolerant capture · conveyor class · full code table | AS733 → |
| AS703 | Payment-box scan chip | Scan-and-announce pipeline · voice pay boxes · counter grade | AS703 → |
| AS810 | Face recognition algorithm chip | 4K@30fps H.264 · liveness check · 40–70 cm class | AS810 → |
| AS812 | Face recognition algorithm chip — high capacity | AS810 family performer · large-site face systems · higher tiers | AS812 → |
| AS569 | Security encryption + fingerprint engine | 1,000-template matcher · TDES/AES/RSA · financial-grade | AS569 → |
Board-level values vary with host configuration; FAE validates against your schematic within 48h. Package and tape/reel options are listed per model page.
Algorithm ownership is the supply chain.
Because the matcher is ours, the roadmap is ours: a liveness improvement reaches the same socket without swapping a device line, and an OEM's firmware survives multiple silicon revisions untouched. 400+ registered patents and software works sit behind that promise.
- Fingerprint security tier — AS608's in-house DSP engine rejects fake fingers at 99.99% company lab rate; sensor pairing is BS-array reference.
- Face processor tier — AS810/AS812 encode 4K@30fps with the liveness verdict on the die, feeding terminal designs up to 50,000 users.
- Decode tier — AS732/AS733 read at 4 mil with 99.9%+ declared decode, in rolling-shutter and motion-tolerant global-shutter flavors.
Designing a chip in your board
Request
Datasheet package and SDK go out to you within 48h of an inquiry.
Schematic review
FAE cross-checks interfaces, decoupling and sensor pairing against your schematic.
SDK demo
Free SDK and demo routines — a working evaluation loop on your bench.
Sample
1–3 days to ship 1 pc or a tray; mixed chip orders welcome.
Mass production
10–25 days below 5,000 pcs with checksum-verified firmware and lot report.
Warranty
2 years, 48h FAE response, and firmware checkpoints through the whole commercial life.
Chip line FAQs
Yes — MOQ is 1 pc per model. Samples ship in 1–3 days with the free SDK, datasheet and demo routines.
BS-series capacitive arrays at 508 DPI class are the reference set; the FAE team confirms your exact sensor model within 48h.
No. The matching, liveness and decode algorithms are part of the chip; the SDK and demo routines are free with every order.
Put a chip design on the bench.
Send the schematic — get the interface review plus a sample offer in 48h, one chip or one reel.
